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SSTUA32866
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications
Rev. 01 -- 15 July 2005 Product data sheet
1. General description
The SSTUA32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM. The SSTUA32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. The SSTUA32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).
2. Features
s s s s s s s s s s s s s s Configurable register supporting DDR2 up to 667 MT/s Registered DIMM applications Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation delay; 2.0 ns max. mass-switching) Supports up to 450 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports SSTL_18 data inputs Checks parity on the DIMM-independent data inputs Partial parity output and input allows cascading of two SSTUA32866s for correct parity error processing Differential clock (CK and CK) inputs Supports LVCMOS switching levels on the control and RESET inputs Single 1.8 V supply operation (1.7 V to 2.0 V) Available in 96-ball, 13.5 x 5.5 mm, 0.8 mm ball pitch LFBGA package
3. Applications
s 400 MT/s to 667 MT/s DDR2 registered DIMMs desiring parity checking functionality
Philips Semiconductors
SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
4. Ordering information
Table 1: Ordering information Tamb = 0 C to +70 C. Type number SSTUA32866EC/G SSTUA32866EC Solder process Package Name Description Version
Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1 ball compound) 96 balls; body 13.5 x 5.5 x 1.05 mm SnPb solder ball compound LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1 96 balls; body 13.5 x 5.5 x 1.05 mm
5. Functional diagram
RESET
CK CK VREF DCKE
SSTUA32866
1D C1 R
QCKEA QCKEB (1)
DODT
1D C1 R
QODTA QODTB (1)
DCS
1D C1 R
QCSA QCSB (1)
CSR
D2
0 1 1D C1 R Q2A Q2B (1)
002aab388
to 10 other channels (D3, D5, D6, D8 to D14)
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUA32866; 1 : 2 Register A configuration with C0 = 0 and C1 = 1 (positive logic)
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
RESET CK CK LPS0 (internal node) D2, D3, D5, D6, D8 to D14 VREF
11
D CLK R D2, D3, D5, D6, D8 to D14
11
CE
D2, D3, D5, D6, 11 D8 to D14
11 11
Q2A, Q3A, Q5A, Q6A, Q8A to Q14A Q2B, Q3B, Q5B, Q6B, Q8B to Q14B
PARITY CHECK C1 0 D CLK R PAR_IN QERR 1 D CLK R CE D CLK R 1 PPO 0
C0
CLK 2-BIT COUNTER R
LPS1 (internal node)
0 D CLK R 1
002aaa650
Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUA32866EC/G
ball A1 SSTUA32866EC index area 123456 A B C D E F G H J K L M N P R T
002aab389
Transparent top view
Fig 3. Pin configuration for LFBGA96
1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 PAR_IN CK CK D8 D9 D10 D11 D12 D13 D14
2 PPO D15 D16 QERR D17 D18 RESET DCS CSR D19 D20 D21 D22 D23 D24 D25
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS n.c. Q8 Q9 Q10 Q11 Q12 Q13 Q14
6 DNU Q15 Q16 DNU Q17 Q18 C0 DNU n.c. Q19 Q20 Q21 Q22 Q23 Q24 Q25
002aab108
Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 PAR_IN CK CK D8 D9 D10 D11 D12 D13 D14
2 PPO DNU DNU QERR n.c. n.c. RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA n.c. Q8A Q9A Q10A Q11A Q12A Q13A Q14A
6 QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB n.c. Q8B Q9B Q10B Q11B Q12B Q13B Q14B
002aab109
Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1)
1 A B C D E F G H J K L M N P R T D1 D2 D3 D4 D5 D6 PAR_IN CK CK D8 D9 D10 DODT D12 D13 DCKE
2 PPO DNU DNU QERR DNU DNU RESET DCS CSR DNU DNU DNU DNU DNU DNU DNU
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD
5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA n.c. Q8A Q9A Q10A QODTA Q12A Q13A QCKEA
6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB n.c. Q8B Q9B Q10B QODTB Q12B Q13B QCKEB
002aab110
Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1)
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
6.2 Pin description
Table 2: Symbol GND Pin description Pin B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3, P4 A4, C3, C4, E3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 A3, T3 H1 J1 G6 G5 G2 LVCMOS input Type ground input Description ground
VDD
1.8 V nominal
power supply voltage
VREF CK CK C0 C1 RESET
0.9 V nominal Differential input Differential input LVCMOS inputs
input reference voltage positive master clock input negative master clock input Configuration control inputs; Register A or Register B and 1 : 1 mode or 1 : 2 mode select. Asynchronous reset input (active LOW). Resets registers and disables VREF data and clock. Chip select inputs (active LOW). Disables D1 to D25 [2] outputs switching when both inputs are HIGH. Data input. Clocked in on the crossing of the rising edge of CK and the falling edge of CK. The outputs of this register bit will not be suspended by the DCS and CSR control. The outputs of this register bit will not be suspended by the DCS and CSR control. Parity input. Arrives one clock cycle after the corresponding data input. Data outputs that are suspended by the DCS and CSR control [3]. Partial parity out. Indicates odd parity of inputs D1 to D25 [2]. Data output that will not be suspended by the DCS and CSR control. Data output that will not be suspended by the DCS and CSR control. Data output that will not be suspended by the DCS and CSR control.
CSR DCS D1 to D25
J2 H2
[1]
SSTL_18 input
SSTL_18 input
DODT DCKE PAR_IN Q1 to Q25, Q2A to Q14A, Q1B to Q14B PPO QCS, QCSA, QCSB QODT, QODTA, QODTB QCKE, QCKEA, QCKEB
[1]
SSTL_18 input SSTL_18 input SSTL_18 input 1.8 V CMOS outputs 1.8 V CMOS output 1.8 V CMOS output 1.8 V CMOS output 1.8 V CMOS output
[1]
G1
[1]
A2
[1]
[1]
[1]
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
Pin description ...continued Pin D2 Type open-drain output Description Output error bit (active LOW). Generated one clock cycle after the corresponding data output Not connected. Ball present but no internal connection to the die. Do not use. Inputs are in standby-equivalent mode and outputs are driven LOW.
Table 2: Symbol QERR
n.c. DNU
[1]
[1]
[1] [2]
Depends on configuration. See Figure 4, Figure 5, and Figure 6 for ball number. Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0. Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1. Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1. Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0. Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1. Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
[3]
7. Functional description
The SSTUA32866 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity, designed for 1.7 V to 2.0 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18 specifications. The error (QERR) output is 1.8 V open-drain driver. The SSTUA32866 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The C0 input controls the pinout configuration for the 1 : 2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH). The SSTUA32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration, parity is checked on the PAR_IN input which arrives one cycle after the input data to which it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after the corresponding data inputs. When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the first device. The PPO and QERR signals are produced on the second device three clock cycles after the corresponding data inputs. The PPO output of the first register is
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
cascaded to the PAR_IN of the second register. The QERR output of the first register is left floating and the valid error information is latched on the QERR output of the second register. If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity check computation. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn and PPO outputs will function normally. The RESET input has priority over the DCS and CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can be hard-wired to ground, in which case, the setup time requirement for DCS would be the same as for the other Dn data inputs. To control the low-power mode with DCS only, then the CSR input should be pulled up to VDD through a pull-up resistor. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the Qn outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTUA32866 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output.
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
7.1 Function table
Table 3: Function table (each flip-flop) L = LOW voltage level; H = HIGH voltage level; X = don't care; = LOW-to-HIGH transition; = HIGH-to-LOW transition Inputs RESET H H H H H H H H H H H H L
[1]
Outputs [1] CK CK L or H L or H L or H L or H X or floating Dn, DODTn, DCKEn L H X L H X L H X L H X X or floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L QCS L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L
DCS L L L L L L H H H H H H X or floating
CSR L L L H H H L L L H H H X or floating
L or H L or H L or H L or H X or floating
Q0 is the previous state of the associated output.
Table 4: Parity and standby function table L = LOW voltage level; H = HIGH voltage level; X = don't care; = LOW-to-HIGH transition; = HIGH-to-LOW transition Inputs RESET H H H H H H H H H H L
[1] [2]
Outputs [1] CK L or H of inputs = H (D1 to D25) even odd even odd even odd even odd X X X or floating PAR_IN [2] L L H H L L H H X X X or floating PPO [3] L H H L L H H L PPO0 PPO0 L QERR H L L H H L L H QERR0 QERR0 H
DCS L L L L H H H H H X
CSR X X X X L L L L H X
CK L or H
X or floating X or floating X or floating X or floating
PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR. Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0. Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1. Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1. PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies. This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
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[3] [4]
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI VO IIK IOK IO ICCC Tstg Vesd Parameter supply voltage receiver input voltage driver output voltage input clamp current output clamp current continuous output current continuous current through each VDD or GND pin storage temperature electrostatic discharge voltage Human Body Model (HBM); 1.5 k; 100 pF Machine Model (MM); 0 ; 200 pF
[1] [2]
Conditions
Min -0.5 -0.5 [1] -0.5 [1]
Max +2.5 +2.5 [2] VDD + 0.5 [2] -50 50 50 100 +150 -
Unit V V V mA mA mA mA C kV V
VI < 0 V or VI > VDD VO < 0 V or VO > VDD 0 V < VO < VDD
-65 2 200
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5 V maximum.
9. Recommended operating conditions
Table 6: Symbol VDD Vref VTT VI VIH(AC) Recommended operating conditions Parameter supply voltage reference voltage termination voltage input voltage AC HIGH-level input voltage data (Dn), CSR, and PAR_IN inputs data (Dn), CSR, and PAR_IN inputs data (Dn), CSR, and PAR_IN inputs data (Dn), CSR, and PAR_IN inputs RESET, Cn RESET, Cn CK, CK CK, CK
[1] [1] [2]
Conditions
Min 1.7 0.49 x VDD Vref - 0.040 0 Vref + 0.250
Typ 0.50 x VDD Vref -
Max 2.0 0.51 x VDD Vref + 0.040 VDD -
Unit V V V V V
VIL(AC)
AC LOW-level input voltage
-
-
Vref - 0.250
V
VIH(DC)
DC HIGH-level input voltage
Vref + 0.125
-
-
V
VIL(DC)
DC LOW-level input voltage
-
-
Vref - 0.125
V
VIH VIL VICR VID
HIGH-level input voltage LOW-level input voltage common mode input voltage range differential input voltage
0.65 x VDD 0.675 600
-
0.35 x VDD 1.125 -
V V V mV
[2]
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
Table 6: Symbol IOH IOL Tamb
Recommended operating conditions ...continued Parameter HIGH-level output current LOW-level output current ambient temperature operating in free air Conditions Min 0 Typ Max -8 8 +70 Unit mA mA C
[1] [2]
The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW.
10. Characteristics
Table 7: Characteristics At recommended operating conditions (see Table 6); unless otherwise specified. Symbol VOH VOL II IDD Parameter HIGH-level output voltage LOW-level output voltage input current static standby current static operating current IDDD Conditions IOH = -6 mA; VDD = 1.7 V IOL = 6 mA; VDD = 1.7 V all inputs; VI = VDD or GND; VDD = 2.0 V RESET = GND; IO = 0 mA; VDD = 2.0 V RESET = VDD; IO = 0 mA; VDD = 2.0 V; VI = VIH(AC) or VIL(AC) Min 1.2 Typ 16 Max 0.5 5 100 40 Unit V V A A mA A
dynamic operating current per MHz, RESET = VDD; clock only VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. IO = 0 mA; VDD = 1.8 V dynamic operating current per MHz, RESET = VDD; per each data input, 1 : 1 mode VI = VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V dynamic operating current per MHz, RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK per each data input, 1 : 2 mode switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V
-
11
-
A
-
19
-
A
Ci
input capacitance, data and CSR inputs input capacitance, CK and CK inputs input capacitance, RESET input
VI = Vref 250 mV; VDD = 1.8 V VICR = 0.9 V; Vi(p-p) = 600 mV; VDD = 1.8 V VI = VDD or GND; VDD = 1.8 V
2.5 2 3
-
3.5 3 4
pF pF pF
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
Table 8: Timing requirements At recommended operating conditions (see Table 6), unless otherwise specified. See Figure 2. Symbol fclock tW tACT tINACT tsu Parameter clock frequency pulse duration, CK, CK HIGH or LOW differential inputs active time differential inputs inactive time setup time DCS before CK, CK, CSR HIGH; CSR before CK, CK, DCS HIGH DCS before CK, CK, CSR LOW DODT, DCKE and data (Dn) before CK, CK PAR_IN before CK, CK th hold time DCS, DODT, DCKE and data (Dn) after CK, CK PAR_IN after CK, CK
[1] [2] [3] This parameter is not necessarily production tested. VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken HIGH. VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
[1] [2] [1] [3]
Conditions
Min 1 0.7 0.5 0.5 0.5 0.5 0.5
Typ -
Max 450 10 15 -
Unit MHz ns ns ns ns ns ns ns ns ns
Table 9: Switching characteristics At recommended operating conditions (see Table 6), unless otherwise specified. See Section 11.1. Symbol fMAX tPDM tPD tLH tHL tPDMSS tPHL tPLH
[1] [2]
Parameter maximum input clock frequency propagation delay, single bit switching propagation delay LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay propagation delay, simultaneous switching HIGH-to-LOW propagation delay LOW-to-HIGH propagation delay
Conditions from CK and CK to Qn from CK and CK to PPO from CK and CK to QERR from CK and CK to QERR from CK and CK to Qn from RESET to Qn from RESET to PPO from RESET to QERR
[1] [2] [1]
Min 450 1.2 0.5 1.2 1 -
Typ -
Max 1.8 1.8 3 2.4 2.0 3 3 3
Unit MHz ns ns ns ns ns ns ns ns
Includes 350 ps of test-load transmission line delay. This parameter is not necessarily production tested.
Table 10: Data output edge rates At recommended operating conditions (see Table 6), unless otherwise specified. See Section 11.2. Symbol dV/dt_r dV/dt_f dV/dt_ Parameter rising edge slew rate falling edge slew rate Conditions from 20 % to 80 % from 80 % to 20 % Min 1 1 Typ Max 4 4 1 Unit V/ns V/ns V/ns
absolute difference between dV/dt_r from 20 % or 80 % and dV/dt_f to 80 % or 20 %
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
10.1 Timing diagrams
RESET
DCS
CSR
m CK
m+1
m+2
m+3
m+4
CK tsu D1 to D25 tPD CK to Q Q1 to Q25 tsu th th
PAR_IN tPD CK to PPO PPO tPD CK to QERR QERR
002aaa655
tPD CK to QERR
Fig 7. Timing diagram for SSTUA32866 used as a single device; C0 = 0, C1 = 0
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
RESET
DCS
CSR
m CK
m+1
m+2
m+3
m+4
CK tsu D1 to D14 tPD CK to Q Q1 to Q14 tsu th th
PAR_IN tPD CK to PPO PPO tPD CK to QERR QERR (not used) tPD CK to QERR
002aaa656
Fig 8. Timing diagram for the first SSTUA32866 (1 : 2 Register A configuration) device used in pair; C0 = 0, C1 = 1
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
RESET
DCS
CSR
m CK
m+1
m+2
m+3
m+4
CK tsu D1 to D14 tPD CK to Q Q1 to Q14 tsu th th
PAR_IN(1) tPD CK to PPO PPO (not used) tPD CK to QERR QERR
002aaa657
tPD CK to QERR
(1) PAR_IN is driven from PPO of the first SSTUA32866 device.
Fig 9. Timing diagram for the second SSTUA32866 (1 : 2 Register B configuration) device used in pair; C0 = 1, C1 = 1
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Product data sheet
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1.8 V DDR2-667 configurable registered buffer with parity
11. Test information
11.1 Parameter measurement information for data output load circuit
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified. The outputs are measured one at a time with one transition per measurement.
VDD DUT TL = 50 CK inputs CK CK test point
RL = 100
TL = 350 ps, 50 OUT
CL = 30 pF(1)
RL = 1000
RL = 1000
002aaa371
test point
(1) CL includes probe and jig capacitance.
Fig 10. Load circuit, data output measurements
LVCMOS VDD RESET VDD/2 tINACT IDD(1) VDD/2 0V tACT 90 % 10 %
002aaa372
(1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA.
Fig 11. Voltage and current waveforms; inputs active and inactive times
tW VIH input VICR VICR VID VIL
002aaa373
VID = 600 mV VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 12. Voltage waveforms; pulse duration
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1.8 V DDR2-667 configurable registered buffer with parity
CK VICR CK tsu input Vref th VIH Vref VIL
002aaa374
VID
VID = 600 mV Vref = VDD/2 VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 13. Voltage waveforms; setup and hold times
CK VICR CK tPLH tPHL VOH output VTT
002aaa375
VICR
Vi(p-p)
VOL
tPLH and tPHL are the same as tPD.
Fig 14. Voltage waveforms; propagation delay times (clock to output)
LVCMOS VIH RESET VDD/2 VIL tPHL VOH output VTT
002aaa376
VOL
tPLH and tPHL are the same as tPD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.
Fig 15. Voltage waveforms; propagation delay times (reset to output)
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Product data sheet
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Philips Semiconductors
SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
11.2 Data output slew rate measurement information
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 50
OUT
CL = 10 pF(1)
test point
002aaa377
(1) CL includes probe and jig capacitance.
Fig 16. Load circuit, HIGH-to-LOW slew measurement
output 80 % dv_f 20 % dt_f
002aaa378
VOH
VOL
Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT
CL = 10 pF(1)
test point
RL = 50
002aaa379
(1) CL includes probe and jig capacitance.
Fig 18. Load circuit, LOW-to-HIGH slew measurement
dt_r VOH 80 % dv_r 20 % output
002aaa380
VOL
Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
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Product data sheet
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1.8 V DDR2-667 configurable registered buffer with parity
11.3 Error output load circuit and voltage measurement information
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
VDD DUT
RL = 1 k
OUT
CL = 10 pF(1)
test point
002aaa500
(1) CL includes probe and jig capacitance.
Fig 20. Load circuit, error output measurements
LVCMOS RESET VCC/2
VCC
0V tPLH VOH 0.15 V
002aaa501
output waveform 2
0V
Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET input.
timing inputs
VICR tHL
VICR
Vi(p-p)
VCC output waveform 1 VCC/2
002aaa502
VOL
Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs
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Product data sheet
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
timing inputs
VICR tLH
VICR
Vi(p-p)
VOH output waveform 2 0.15 V
002aaa503
0V
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs
11.4 Partial parity out load circuit and voltage measurement information
VDD = 1.8 V 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z0 = 50 ; input slew rate = 1 V/ns 20 %, unless otherwise specified.
DUT
OUT
CL = 5 pF(1)
test point
RL = 1 k
002aaa654
(1) CL includes probe and jig capacitance.
Fig 24. Partial parity out load circuit
CK VICR CK tPLH tPHL VOH output VTT
002aaa375
VICR
Vi(p-p)
VOL
VTT = VDD/2 tPLH and tPHL are the same as tPD. Vi(p-p) = 600 mV
Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock inputs
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Product data sheet
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
LVCMOS VIH RESET VDD/2 VIL tPHL VOH output VTT
002aaa376
VOL
VTT = VDD/2 tPLH and tPHL are the same as tPD. VIH = Vref + 250 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS inputs. VIL = Vref - 250 mV (AC voltage levels) for differential inputs. VIL = VDD for LVCMOS inputs.
Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to RESET input
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Product data sheet
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
12. Package outline
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
D
B
A
ball A1 index area
A E
A2 A1 detail X
e1
1/2 e
C
v M C A B
e T R P N M L K J H G F E D C B A ball A1 index area
y1 C
y
b
w M C
e
e2
1/2 e
123456 X 0 5 scale 10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 13.6 13.4 e 0.8 e1 4 e2 12 v 0.15 w 0.1 y 0.1 y1 0.2
OUTLINE VERSION SOT536-1
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 00-03-04 03-02-05
Fig 27. Package outline SOT536-1 (LFBGA96)
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
13.5 Package related soldering information
Table 11: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Product data sheet
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
14. Abbreviations
Table 12: Acronym CMOS DDR DIMM LVCMOS PPO PRR RDIMM SSTL Abbreviations Description Complementary Metal Oxide Silicon Double Data Rate Dual In-line Memory Module Low Voltage Complementary Metal Oxide Silicon Partial Parity Out Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic
15. Revision history
Table 13: Revision history Release date 20050715 Data sheet status Product data sheet Change notice Doc. number 9397 750 14759 Supersedes Document ID SSTUA32866_1
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Product data sheet
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
16. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
19. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
20. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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Product data sheet
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SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
21. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 10.1 11 11.1 11.2 11.3 11.4 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Recommended operating conditions. . . . . . . 10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 13 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Parameter measurement information for data output load circuit . . . . . . . . . . . . . . . . . . 16 Data output slew rate measurement information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Error output load circuit and voltage measurement information . . . . . . . . . . . . . . . . 19 Partial parity out load circuit and voltage measurement information . . . . . . . . . . . . . . . . 20 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 24 Package related soldering information . . . . . . 24 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 26 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Contact information . . . . . . . . . . . . . . . . . . . . 26
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 15 July 2005 Document number: 9397 750 14759
Published in The Netherlands

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